One of the well-known problems presented by the increased device count and complexity of modern VLSI chips is the difficulty in getting them debugged and qualified for full production. Once the initial design is completed and A-step parts are obtained, engineers are faced with the necessity of fixing any circuit, logic, or microcode bugs, as well as improving the device operating frequency and test coverage. All too often these tasks are delegated to a small number of people from the original design team, many of whom may have moved on to other projects or other companies, or the tasks may be delegated to other people less familiar with the chip. Thus, the people charged with making the part into a saleable product may or may not have an in-depth understanding of the full chip and the complex interactions between its component units. Even for someone who has a thorough understanding of the device and knows where to look when isolating a particular problem, the lack of internal-state observables and the high cost of obtaining it only compounds the problem. Writing product validation (PV) tests can be very difficult for an engineer unfamiliar with a unit or the whole chip, since the state of each targeted node must be carefully propagated through unfamiliar territory to the pins where it can be observed. The process of fault grading is much less painful when important internal signals can be easily seen.
In the past, the problem of observing internal signals while debugging has been solved solely by probing or E-beam scanning. Both of these techniques are limited to unpassivated dice, are difficult for customer-returned packaged parts and are not time-efficient for those unfamiliar with the chip. Knowing where to start looking for a bug is half of the battle. More recently, much attention has been given to designed-in approaches to controllability and observables, such as scan-in/scan-out and linear-feedback shift registers (LFSRs), but these mechanisms have limitations.
Conventional scan logic introduces increased path delay and requires that the tested part be exercised at a reduced clock frequency while scanning.
Linear-feedback shift registers (LFSRs) in general use an algorithm to compress their input data into a more convenient representative signature, which can be compared with an expected value to detect the presence of errors in the input data. The cells of the register are representative of a binary polynomial P(x), since the output of the register is fed back to selected cell positions. Clocking the register effectively multiplies the polynomial representing the contents of the register by x and divides this by the feedback polynomial P(x); both operations are modulo-2. In practice this is implemented by shifting the register contents and feeding back the most-significant bit of the shift register, the quotient bit, to be XORed with the register contents in the bit cell positions determined by the coefficients of P(x). What remains in the register after all input bits are processed is the modulo-2 remainder of the modulo-2 division, called the signature. By carefully choosing the feedback polynomial, various levels of error detection may be obtained; however, a given implementation is able to detect only a limited number of erroneous bits that occur in certain patterns. All LFSRs have the potential of allowing errors to go undetected, if those errors happen to map to the same signature as the correct pattern.
LFSRs have the drawback that the process destroys all individual bit information and LSFRs are limited in error-detecting effectiveness by the choice of a particular feedback polynomial. This technique also requires test code to periodically compare the accumulated value of an internal signature with a stored predicted value to determine the presence or absence of errors. It does not pin point those errors to exact locations.
It is an object of the invention to provide an improved method and means for testing and debugging the internal components of a very large scale integrated (VLSI) circuit chip.